1. Field of the Invention
The present invention relates to random access memory (RAM). More particularly, the present invention relates to RAM blocks suitable for use in field programmable gate array (FPGA) architectures.
2. The Prior Art
Modern FPGAs generally contain blocks of RAM. Each RAM block has address and data inputs, data outputs, a write enable input and often also a read enable input. When read enable is deasserted, the outputs of the RAM block are held in the previous state. This avoids adding any delay to the read path, or consuming dynamic power to disable it. Deasserting read enable may also be used to power down some circuitry, such as sense amplifiers.
Since the RAM blocks in an FPGA of necessity have a fixed capacity, customers who need higher RAM capacity must gang multiple RAM blocks together. For instance, an FPGA may provide RAM blocks capable of storing 8 Kbits in either a 4K-word×2-bit or 1K-word×8-bit format. In a design to be programmed into the FPGA that requires a RAM that is arranged as 4K words×8 bits, it is required that four RAM blocks be combined.
One way to combine RAM blocks to achieve the desired capacity is to configure the four blocks in 4K-word×2 bit format, with each block producing 2 of the 8 output bits. This provides the minimal delay as no extra logic is required in the speed path. However since all RAM blocks must be enabled for every read operation, the dynamic power will be that of four RAM blocks.
An alternative way to combine RAM blocks to achieve the desired capacity is shown in FIG. 1, which is generally preferred in low power applications. Composite RAM block 10 is configured from RAM blocks 12, 14, 16, and 18, each block arranged in 1K-word×8-bit format. RAM blocks 12, 14, 16, and 18 share address bits A0-A9. Additional address bits A10 and A11 are then used as the select inputs of an 8-bit wide 4-input multiplexer 28 which selects the output of one of the RAM blocks 12, 14, 16, and 18 to be used. To save power, each block can be enabled only when the corresponding values of A10 and A11 are present. This is achieved by means of AND gates 20, 22, 24 and 26. AND gates 20, 22, 24, and 26 are “soft gates” created by programming the programmable logic resources in the FPGA as is known in the art. Table 1 shows the combinations of address inputs A10 and A11 that enable the individual ones of RAM blocks 12, 14, 16, and 18.
TABLE 1A10A11RAM Block Enabled00RAM Block 1201RAM Block 1410RAM Block 1610RAM Block 18
The total dynamic power in the configuration shown in FIG. 1 is thus the same as the power consumed if only one of the blocks was present in the design, but some additional delay in the speed path is incurred due to the insertion of one of AND gates 20, 22, 24, and 26 to decode A10 and A11 to produce the enable signal for each of RAM blocks 12, 14, 16, and 18. Another delay is incurred by the 4-input multiplexer 28 positioned to pass only the output of the enabled one of RAM blocks 12, 14, 16, and 18. Another disadvantage is that the additional logic (AND gates 20, 22, 24, 26 and multiplexer 28) must be provided by programming soft gates in the FPGA.
The prior art circuit of FIG. 1 is similar to one shown in Tessier, Betz, Neto, Gopalsamy, Power-aware RAM Mapping for FPGA Embedded Memory Blocks, Int'l Symp. FPGAs, 2006, pp. 189-198.
U.S. Pat. No. 6,049,487 discloses and claims RAM arrays having multiple read enables, but only in combination with tristate outputs and an output enable scheme. Tri-state signals are disadvantageous in state-of-the-art FPGAs due to their greater complexity and the possibility of conflicting drivers.